This invention relates to programmable logic arrays (PLA's); and more particularly, it relates to PLA's which consume a reduced amount of power and occupy a reduced amount of chip space.
In general, a PLA is a logic circuit which receives a plurality of digital input signals and generates a plurality of digital output signals wherein each of the digital output signals is a programmable sum-of-product combination of the input signals. In conventional PLA's, one circuit is provided for generating a plurality of terms which are the logical AND of selected input signals; and another circuit is provided to generate the output signals by selectively ORing the AND terms. A typical PLA may have a total of 30 input signals, generate a total of 60 AND terms from the input signals, and generate a total of 30 output signals by selectively ORing the 60 AND terms.
One article which describes PLA's in greater detail is "Field-PLA's Simplify Logic Designs", Electronic Design 18, Sept. 1, 1975, pages 84-90. See also a technical data sheet from Signetics Corporation on their 82S104 and 82S105 PLA chips entitled "Bipolar Field Programmable Logic Sequencer - 82S104 (O.C.)/82S105 (T.S.)", dated August, 1980. A detailed circuit diagram of the PLA described in the former is given on page 86 and a detailed circuit diagram of the PLA described in the latter is given at page 6.
These PLA's of the prior art, along with the power that they consume and the chip space that they occupy, are described in greater detail herein in conjunction with FIGS. 2, 3, and 4. And this analysis will show that by comparison, the PLA's of the present invention use substantially less power and occupy substantially less chip space.
Accordingly, a primary object of the invention is to provide an improved programmable logic aray.
Another object of the invention is to provide a programmable logic array which dissipates substantially less power than PLA's of the prior art.
Still another object of the invention is to provide a programmable logic array which occupies substantially less chip space than PLA's of the prior art.